Principal Physical Design Engineer United States Washington Redmond

This role leads the physical design methodology and tool flow for block, sub-chip, and full-chip levels, focusing on Place and Route, Static Timing Analysis, and Physical Verification. The incumbent develops convergence recipes, implements global clocking schemes, and manages IP collateral installation while guiding junior engineers through design reviews. Success requires deep expertise in semiconductor design principles, EDA tools, and scripting to deliver high-quality ASIC products.