Principal Physical Design Engineer

This role seeks a highly skilled Physical Design Flow and Place-and-Route Development Engineer to drive methodology, automation, and implementation solutions for advanced ASIC designs. The position involves developing scalable P&R methodologies, improving flow robustness, and partnering with design teams to deliver high-quality, high-performance silicon using Cadence and Synopsys tools. Key activities include automating flow steps with Tcl and Python, supporting full-chip P&R execution, and ensuring physical design quality metrics are met.