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Principal Physical Design Engineer at Astera Labs - ApplyBlast

Principal Physical Design Engineer

Astera Labs

3 days ago

4.3 on Glassdoor

Bengaluru, Karnataka, India

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Principal Physical Design Engineer to lead the development of complex SoC and silicon products for server, storage, and networking applications. The role involves full chip or block level ownership from architecture to GDSII, utilizing advanced physical design tools and methodologies for technologies 16nm or less. The ideal candidate will have a strong background in electrical engineering and extensive experience in synthesis, timing closure, and physical verification.

Responsibilities

Drive complex SoC designs from architecture to GDSII production
Perform synthesis, timing closure, and formal verification at block and full-chip levels
Utilize physical design tools and flows for technologies 16nm or less

Skills

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

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Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.