Principal RTL Design Engineer

Marvell seeks a Principal Design Engineer to lead micro-architecture and RTL development for next-generation System-on-Chips (SoCs) in enterprise, cloud, and AI domains. This role involves defining subsystem-level designs, collaborating with cross-functional teams on verification and physical design, and solving complex timing and power issues in advanced 3nm or 2nm process nodes. Responsibilities include owning RTL implementation, mentoring junior engineers, and driving designs from concept through tape-out readiness.