Hewlett Packard Enterprise
This role involves performing high-speed ASIC PAM4 SerDes and system-level signal and power integrity analysis for cutting-edge networking product design. The position requires expertise in channel margin analysis, PCB timing analysis, and correlating simulation results with measurements to improve design accuracy. The engineer will collaborate with cross-functional teams to implement design rules and optimize system performance.
Headquarters
The Woodlands, Texas, United States
Company Size
10001+ employees
Founded
1939
Discover HPE edge-to-cloud, enterprise compute IT, data, and security solutions. Learn how HPE empowers digital transformation through AI and sustainability.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Hewlett Packard Enterprise.
Hewlett Packard Enterprise Announces $2 Billion Debt Offering
17 hours ago
Senior Signal Integrity Design Engineer
NVIDIA
System Signal/Power Integrity Engineer
Broadcom
Signal Integrity Design Engineer
oraclecloudinfrastructure
Senior Signal Integrity Engineer – LPU Packaging
NVIDIA
Signal Integrity Engineer
oraclecloudinfrastructure
Signal Integrity Engineer
oraclecloudinfrastructure