Principal Silicon Design Verification Engineer United States California Mountain View

This role involves owning the development of C and C++ based test content for subsystem and SoC levels, including bare-metal bring-up and complex multi-IP flows. The candidate will architect SystemVerilog and UVM environments, drive pre-silicon verification strategies, and mentor engineers within the verification team. Responsibilities include building test infrastructure, establishing coverage signoff criteria, and collaborating with architecture, design, and firmware teams to ensure successful silicon bring-up.