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Principal Software Engineer (Verification of VIP using Verilog/SV/UVM ) at Cadence - ApplyBlast

Principal Software Engineer (Verification of VIP using Verilog/SV/UVM )

Cadence

9 months ago

4.0 on Glassdoor

Ahmedabad, India

Onsite

Full Time

Senior

0 applicants

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About this role

Cadence is hiring a verification engineer in Ahmedabad to work on Verification IP (VIP) in the electronic design automation domain. The role focuses on delivering high-quality verification solutions for advanced protocols and supporting customer needs within a collaborative, innovation-driven environment. The position is intended for an experienced professional who can ramp quickly on new technologies and work effectively across teams.

Skills

Qualifications

B.TechM.Tech

About Cadence

cadence.com

Headquarters

San Jose, California, United States

Company Size

10001+ employees

Founded

1988

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Cadence is a company specializing in electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries. Their tools enable design and verification of integrated circuits, systems on chips, and electronics systems, streamlining the development process for engineers and designers. With a commitment to innovation and excellence, Cadence empowers companies to enhance product performance and reduce time to market through advanced simulation, verification, and design tools.