R&D Engineer IC Design

A Memory Design Validation Engineer leads the verification of SRAM and custom macro compilers in cutting-edge 2nm process technologies within Broadcom's Central Engineering Group. The role involves performing functional, signal integrity, and transistor-level simulations to resolve design discrepancies and ensure accurate timing and power models. Collaborating with design and modeling teams, the engineer develops automated scripts and supports silicon debug efforts to validate complex memory architectures.