About this role
The RTL & Codesign Engineer at OpenAI is responsible for designing and implementing critical compute, memory, and interconnect components for AI accelerators. This hands-on role includes producing production-quality RTL in Verilog/SystemVerilog, collaborating with various teams to ensure efficient hardware/software co-design, and participating in architectural studies and design reviews. The engineer will also validate design intent through performance and functional models while ensuring compliance with functional correctness and timing requirements throughout the silicon lifecycle.
Required Skills
- RTL Design
- Microarchitecture
- Performance Modeling
- Feasibility Analysis
- Hardware/Software Co-Design
- Functional Correctness
- Timing Closure
- Design Reviews
- Documentation
- Silicon Lifecycle
+14 more
About OpenAI
openai.comThe company specializes in providing innovative solutions to enhance online experiences for businesses and consumers. It offers a range of products and services designed to streamline operations, improve customer engagement, and drive growth in the digital landscape. With a focus on user experience and cutting-edge technology, the company aims to empower businesses to thrive in a rapidly evolving market.
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