Senior Analog Engineering Manager

The Senior Analog Engineering Manager leads the development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs, combining deep technical expertise in high-speed memory interfaces with strong people leadership. This role involves managing a team responsible for the end-to-end delivery of high-performance, low-power DDR PHYs, from architecture through silicon bring-up, while shaping the roadmap for DDR6-class signaling and architecture. The position requires driving technical oversight, program execution, and cross-functional collaboration to ensure successful delivery and future readiness.