Senior Applications Engineer – DDR Design IP

BETA CAE Greece(4 months ago)

San Jose, CAOnsiteFull TimeSenior$84,000 - $156,000Engineering

About this role

The Senior Applications Engineer – DDR Design IP at Cadence is part of the IP team that develops industry-leading IPs for various markets including data centers, automobiles, and wireless systems. This role focuses on supporting technical presales of DDR IP, generating collateral through simulations and publications, and leveraging knowledge of memory interface standards to architect memory solutions for customers. It offers opportunities for both technical growth and business skill development within a collaborative environment.

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Required Skills

Technical Presales
DDR IP
Verilog Simulations
Presentation Skills

Qualifications

BS in EE
MS in EE
Computer Architecture
Electronics Circuits
Verilog HDL

About BETA CAE Greece

beta-cae.com

BETA CAE Systems is a leading provider of advanced simulation software solutions that cater to the needs of engineers and researchers in various fields, including automotive, aerospace, and manufacturing. With a comprehensive suite of tools for computer-aided engineering (CAE), BETA empowers users to effectively perform tasks related to finite element analysis (FEA), computational fluid dynamics (CFD), and process automation. Recently acquired by Cadence, the company continues to innovate in areas such as machine learning and predictive analysis, bolstering its commitment to enhancing product design and simulation accuracy.

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