Senior ASIC Engineer

This role focuses on the architecture and RTL design of next-generation Power Management Unit (PMU) IP for NVIDIA's diverse product lines, including data centers, GeForce, automotive, and personal computing. The position involves collaborating with software and power architecture teams to define micro-architectures for power features and supporting silicon debug to ensure optimal chip performance and efficiency. The engineer will implement designs that manage thermal, active, and low-power control logic across various workloads.