Senior ASIC Physical Design Engineering Technical Leader

The Senior ASIC Physical Design Engineering Technical Leader drives the full RTL-to-GDSII implementation process for innovative hardware platforms powering Cisco's core networking products. This role involves optimizing design methodologies, ensuring timing and power integrity convergence, and leading technical strategies for advanced process node tapeouts. The position requires deep expertise in physical design flows, EDA tools, and cross-functional collaboration to deliver high-performance silicon solutions.