Senior ASIC Physical Layout Engineer

This role involves leading top-level physical layout integration for advanced mixed-signal ASICs and driving floorplanning, chip finishing, and physical verification through to successful tape-out. The position requires collaborating with analog, RF, digital, and system designers to contribute to ultra-low-power SoCs, imaging devices, and advanced RF technologies. It offers the opportunity to shape physical design methodologies and layout best practices within a collaborative, internationally recognized Swiss engineering organization.