Senior ASIC/SoC Verification Architect

This role requires a highly experienced professional with 20-25 years in ASIC/SoC verification to define verification strategies, develop full-chip test plans, and architect UVM-based testbenches. The position involves leading end-to-end verification projects, from micro-architecture specifications to tape-out sign-off, while mentoring engineering teams and collaborating with cross-functional stakeholders. Key responsibilities include executing gate-level simulations, managing regressions, and driving verification closure for next-generation semiconductor products.