Senior Design Verification Engineer - CXL/PCIe

Astera Labs

3 months ago

4.3 on Glassdoor

Bengaluru, India

Hybrid

Full Time

Senior

0 applicants

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About this role

A Senior Design Verification Engineer at Astera Labs focuses on ensuring the functional correctness and compliance of complex connectivity SoCs used in rack-scale AI infrastructure, particularly for PCIe and CXL protocols. The role supports silicon development for server, storage, and networking applications and collaborates with cross-functional teams to deliver robust, scalable designs.

Skills

Qualifications

BS in Electrical EngineeringBS in Computer EngineeringMS Preferred

About Astera Labs

asteralabs.com

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.