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Senior Design Verification Engineer at Astera Labs - ApplyBlast

Senior Design Verification Engineer

Astera Labs

1 month ago

4.3 on Glassdoor

Toronto, Ontario, Canada

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Senior Design Verification Engineer to build and validate complex connectivity silicon for next-generation AI infrastructure. The role involves developing scalable verification environments, integrating UVM and C/C++ workflows, and collaborating with RTL designers to resolve issues across simulation and emulation. This position contributes to delivering reliable, high-bandwidth products that connect CPUs, GPUs, memory, storage, and networking devices in rack-scale AI systems.

Responsibilities

Build and maintain UVM-based verification environments using SystemVerilog and C/C++
Create directed and constrained-random tests and analyze coverage data
Collaborate with RTL designers to debug and resolve failures across simulation and emulation

Skills

Qualifications

Bachelor's degree in Electrical Engineering

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

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Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.