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Senior Design Verification Engineer at Astera Labs - ApplyBlast

Senior Design Verification Engineer

Astera Labs

25 days ago

4.3 on Glassdoor

San Jose, California, United States

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is seeking a Senior Design Verification Engineer to define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. The role involves partnering with RTL, architecture, and post-silicon teams to build verification strategies for complex switching behavior across high-bandwidth protocols. This position offers the opportunity to own meaningful verification challenges within the CCE2 team, contributing to the development of highly reliable PCIe and UALink connectivity products.

Responsibilities

Develop block- and subsystem-level verification plans from specifications and architecture
Build and enhance reusable UVM-based SystemVerilog testbenches and agents
Drive functional and code coverage analysis to close verification gaps

Skills

Qualifications

Bachelor's degree in Electrical EngineeringBachelor's degree in Computer Engineering

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.