Senior DFT Engineer
BETA CAE Greece(1 year ago)
About this role
A SoC/ASIC Digital Design Engineer at Cadence is responsible for working on Design for Test (DFT) aspects, including scan chain insertion and automatic test pattern generation. The role requires collaboration with cross-functional teams and a focus on quality metrics for effective pattern generation, ensuring high design test coverage and fault analysis.
Required Skills
- DFT
- ATPG
- MBIST
- Verilog
- Synthesis
Qualifications
- Department of Defense Clearance
About BETA CAE Greece
beta-cae.comBETA CAE Systems is a leading provider of advanced simulation software solutions that cater to the needs of engineers and researchers in various fields, including automotive, aerospace, and manufacturing. With a comprehensive suite of tools for computer-aided engineering (CAE), BETA empowers users to effectively perform tasks related to finite element analysis (FEA), computational fluid dynamics (CFD), and process automation. Recently acquired by Cadence, the company continues to innovate in areas such as machine learning and predictive analysis, bolstering its commitment to enhancing product design and simulation accuracy.
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