Astera Labs
The Senior Digital Design Engineer designs and integrates high-performance connectivity silicon for next-generation AI infrastructure, contributing to architecture, RTL implementation, and timing closure for PCIe and Ethernet controllers. This role involves collaborating with cross-functional teams to deliver robust, production-ready designs at advanced process nodes, ensuring reliable, high-bandwidth connections within rack-scale AI systems. The position aims to improve product quality, accelerate time to market, and strengthen customer confidence through precise design execution and integration.
Headquarters
Santa Clara, California, United States
Company Size
201-500 employees
Founded
2017
Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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