Senior Engineer – Silicon-to-System Power Delivery & Integrity

This role leads research and methodology development in power delivery and power integrity, focusing on the interactions between SoC silicon power characteristics and package to board power delivery architectures. The position involves developing custom modeling methodologies, computational frameworks, and cross-layer optimization strategies to address SoC power delivery challenges in next-generation high-performance computing platforms. The engineer will work on defining target impedance, optimizing board-level PDN architectures, and validating computational frameworks that integrate SoC load behavior with system-level models.