accelercomm
The Senior Hardware Design Engineer will develop RTL implementations for FPGA and ASIC platforms, collaborating with algorithm and system architecture teams to create and validate micro-architectures for space‑qualified communication devices. The role involves design, verification, and integration of high‑throughput signal processing hardware while adhering to AccelerComm's engineering processes.
Headquarters
Southampton, England, United Kingdom
Company Size
51-200 employees
Founded
2016
AccelerComm provides high-performance physical layer IP for 5G and beyond, focused on satellite, terrestrial, and hybrid networks. Its solutions include AX-RG regenerative NTN, AX-TP transparent/hybrid NTN, and embedded LDPC FEC IP, all designed to maximize network performance and efficiency. The company emphasizes substantial data-per-watt advantages over software-only approaches to enable energy-efficient, scalable networks. Overall, AccelerComm offers proven PHY IP that underpins next-generation communications for operators and equipment providers.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for accelercomm.
accelercomm didn’t post a salary, so this is our estimate from similar listings.
Principal Engineer ASIC / Sr. Principal Engineer ASIC
Northrop Grumman
Principal Digital Design Engineer
NXP Semiconductors
Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)
General Dynamics Mission Systems, Inc
Advanced ASIC FPGA Engineer
General Dynamics Mission Systems, Inc
ASIC & FPGA Design Engineer
Lockheed Martin
Digital Design Engineer (Mid-Senior Level)
Movandi