Senior Layout Engineer – DPG LPDDR

This role focuses on Place & Route and Physical Design for digital or semi-custom blocks, developing floorplans and placement strategies to achieve timing, power, and congestion closure. Candidates will execute placement, CTS, and routing using industry-standard tools while fixing DRC, LVS, and EM/IR violations to ensure signoff-clean designs. The position also involves performing full-chip and block-level Static Timing Analysis (STA) across various modes and corners to drive timing closure strategies.