About this role
NVIDIA is seeking a Senior Mask Layout Design Engineer to perform physical layout for high-speed mixed-signal circuits such as PLLs and I/O circuits in advanced CMOS technologies. The role involves collaborating with engineers to customize designs, ensure compliance with design rules, and verify layouts using specialized tools.
Required Skills
- Cadence
- Virtuoso
- DRC
- LVS
- Python
- Perl
- Hercules
- Calibre
- PrimeYield
- Layout Design
About NVIDIA
nvidia.comNVIDIA invents the GPU and drives advances in AI, HPC, gaming, creative design, autonomous vehicles, and robotics.
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