Senior Mask Layout Design Engineer

NVIDIA is seeking a Senior Mask Layout Design Engineer to handle challenging high-speed mixed-signal circuit designs in state-of-the-art sub-micron CMOS technologies. The role involves performing physical layout for functions like PLLs and high-speed I/O circuits, customizing designs for VLSI products, and collaborating with ASIC and mixed-signal engineers. This position requires expertise in Cadence tools and verification flows to ensure designs meet design rules and schematics.