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taiwansemiP1
The Senior Memory Layout Engineer at TSMC Design Technology Canada Inc. is responsible for advanced custom layout design and R&D projects on cutting-edge CMOS/FinFET processes. This role involves implementing high-speed and high-density memory compilers and analog circuits while ensuring compliance with industry standards for verification and extraction. The position requires strong expertise in layout techniques, CAD tools, and scripting to deliver high-quality designs independently.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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and employee contacts for taiwansemiP1.
taiwansemiP1 didn’t post a salary, so this is our estimate from similar listings.
29% below the average for this role