Senior Photonic Layout Design Engineer

This role involves collaborating with a multi-disciplinary team to handle high-speed mixed-signal and Silicon Photonic designs. The position focuses on chip layout, circuit design, verification, and physical layout for mixed-signal functions using state-of-the-art CMOS technologies. The engineer will work closely with Silicon Photonic and mixed-signal engineers to customize designs for integration into SiPh and SERDES products.