Senior Physical Design Engineer
Astera Labs(4 days ago)
About this role
Astera Labs is looking for a Senior Physical Design Engineer to lead the physical implementation of advanced high-speed transceiver IPs in cutting-edge semiconductor nodes. The role involves coordinating with cross-functional teams to optimize design performance, power, and timing for next-generation chip architectures.
Required Skills
- Physical Design
- Floor Planning
- Timing Closure
- Signoff Checks
- Scripting
Qualifications
- Bachelor’s or Master’s in Electrical Engineering
- 4+ years experience in physical design
- Experience with Synopsys ICC2, Cadence Innovus, Calibre, Voltus
About Astera Labs
asteralabs.comAstera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.
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