Senior Physical Design Methodology Engineer, PPA Fusion Compiler

A Senior Physical Design Methodology Engineer (PPA Fusion Compiler) at NVIDIA works within the Networking Silicon engineering team to advance physical design methodologies for GPUs and high-speed communication SoCs. The role supports NVIDIA’s chip development by focusing on improving performance, power, and area (PPA) and applying machine-learning techniques to methodology and automation. The position contributes to industry-leading silicon in a collaborative, innovation-driven environment.