Senior Physical Design Methodology Engineer, PPA Fusion Compiler
NVIDIA(1 month ago)
About this role
A Senior Physical Design Methodology Engineer (PPA Fusion Compiler) at NVIDIA works within the Networking Silicon engineering team to advance physical design methodologies for GPUs and high-speed communication SoCs. The role supports NVIDIA’s chip development by focusing on improving performance, power, and area (PPA) and applying machine-learning techniques to methodology and automation. The position contributes to industry-leading silicon in a collaborative, innovation-driven environment.
Required Skills
- Physical Design
- PPA
- Machine Learning
- Floorplanning
- Clock Distribution
- Power Distribution
- Place-and-Route
- Timing Analysis
- Scripting
- Verification
+3 more
Qualifications
- MS in Electrical Engineering
- MS in Computer Engineering
- MS in Computer Science
About NVIDIA
nvidia.comNVIDIA invents the GPU and drives advances in AI, HPC, gaming, creative design, autonomous vehicles, and robotics.
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