Senior Principal Engineer, Design Verification

France Cars SAS AAA(20 hours ago)

United States, San Jose, California, CaliforniaOnsiteFull TimeSenior$221,500 - $326,300

About this role

Altera is a leading FPGA company focused on accelerating programmable compute in AI, networking, and edge domains. They are seeking a highly experienced Senior Principal Engineer to lead design verification of high-performance silicon solutions for data center and networking applications.

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Required Skills

Verilog
SystemVerilog
UVM
PCIe
ASIC
SoC
Debugging
Verification
FPGA
High-Performance Computing

Qualifications

Bachelor’s degree in Computer Engineering, Electrical Engineering, or related field
20+ years of experience in ASIC/SoC design verification
Expertise in PCIe protocols and complex SoC subsystems
20+ years in SystemVerilog, UVM, and testbench development
Track record of delivering Silicon in networking and HPC applications

About France Cars SAS AAA

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Bloomberg is a global leader in financial information and technology, providing data, news, and analytics to financial professionals around the world. The company offers an array of products and services, including the Bloomberg Terminal, which delivers real-time data and insights for trading, investment, and risk management. With a commitment to innovation, Bloomberg combines cutting-edge technology with extensive market expertise to empower financial professionals in making informed decisions.

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