Senior SOC Timing Engineer
Altera
About this role
An SOC Timing Engineer working on timing closure and signoff for FPGA/SoC and subsystem designs at advanced process nodes. Based in Penang, Malaysia, the role sits within semiconductor physical design engineering supporting projects at 10nm and below.
Skills
Qualifications
BE Electronics EngineeringMS Electronics EngineeringPhD Electronics Engineering
About Altera
altera.comAltera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
Salary
$170k – $228k
per year