Senior Staff Design Engineer - Memory Subsystem COE

A Senior RTL Design Engineer at Marvell designs and verifies DDR/LPDDR/HBM IP subsystems within the Center of Excellence, driving architecture definition, RTL implementation, and integration for hyperscale cloud and AI chips. The role involves close collaboration with architecture, verification, and physical design teams to ensure high-performance, low-latency data paths and reliable silicon bring-up.