Senior Staff Design Verification Engineer – Memory Sub-System (DDR/LPDDR/HBM )

A Verification Engineer at Marvell specializes in the Center of Excellence, designing and delivering production-ready IP subsystems for high-performance data center, cloud, and AI applications. The role focuses on developing UVM/System Verilog verification environments, creating test benches for memory interfaces, and collaborating with design and firmware teams to ensure silicon compliance and coverage.