Senior Staff Engineer - Design Verification

As a Senior RTL Verification Engineer at Marvell, you will architect and implement simulation test benches using UVM to verify custom silicon designs for high-performance data center networking and computing. You will own the development of comprehensive test plans, debug complex simulation failures, and collaborate closely with logic designers to ensure coverage closure and design correctness. This role involves deep technical work with hardware verification languages, object-oriented methodologies, and gate-level simulations to deliver optimized and reliable semiconductor solutions.