Senior Staff Verification Engineer For Worldguard

A Senior Digital Verification Engineer at SiFive ensures chip reliability by defining verification plans, designing testbenches using SystemVerilog and UVM, and driving coverage closure for complex RISC-V processor architectures. The role involves deep debugging of RTL failures, generating constrained-random stimuli, and validating security architectures across various protocols like AXI. Collaboration spans architectural analysis and integration of third-party verification IPs to support cutting-edge compute platforms.