Senior Validation Engineer – High-Speed PCB Design & Signal Integrity (25G+)

The Senior Validation Engineer designs and validates high-speed PCBs for next-generation silicon devices operating at data rates of 25Gbit/s and beyond. This role involves schematic capture, layout, and signal integrity analysis using Cadence Allegro, alongside lab characterization and test automation. The position requires close collaboration with design and product teams to shape validation strategies and influence product development.