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Silicon Validation Engineer at MatX - ApplyBlast

Silicon Validation Engineer

MatX

2 months ago

Mountain View, California, United States

Hybrid

Full Time

Senior

0 applicants

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About this role

MatX is seeking a Silicon Validation Engineer to own silicon bring-up and validation from first power‑on through production readiness. The role involves developing validation plans, debugging complex cross‑functional failures, and collaborating with architecture, design, DV, firmware, and product teams to ensure performant and reliable silicon for high‑performance GenAI workloads.

Responsibilities

Own silicon bring‑up and validation from first power‑on to production readiness
Develop and execute validation plans for chip‑level and SiP‑level functionality and performance
Debug complex cross‑functional failures using logs, registers, waveforms, and lab equipment

Skills

About MatX

matx.com

Headquarters

Mountain View, California, United States

Company Size

1-10 employees

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MatX designs high-throughput chips and systems purpose-built for large transformer AI models, with their MatX One chip delivering leading FLOPS/mm2, low-latency decode, and the most scale-up interconnect of any announced product. Supporting clusters of hundreds of thousands of chips, MatX targets training, RL, and inference workloads for large dense and MoE models with no upper limit on model size, serving the large model needs of frontier labs. MatX provides a programming model that gives users direct hardware control, with weights typically in SRAM for low latency and KVs in HBM for long-context support.