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Sr. Principal Design Engineer at Cadence - ApplyBlast

Sr. Principal Design Engineer

Cadence

5 months ago

4.0 on Glassdoor

Hyderabad

Onsite

Full Time

Senior

0 applicants

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About this role

A Senior Verification Engineer at Cadence leads verification strategy for SOC or Chiplet-based designs, developing comprehensive test plans using SystemVerilog and UVM methodologies. The role focuses on mentoring teams, executing coverage-driven verification cycles, and collaborating with design architects to ensure high-quality silicon delivery.

Responsibilities

Lead verification strategy for complex SOC and chiplet-based designs
Develop comprehensive test plans and verification environments using UVM
Create bus functional models, monitors, checkers, and scoreboards
Execute coverage-driven verification closure cycles
Mentor verification engineers and foster technical excellence within the team

Skills

Qualifications

BTech in EngineeringMTech in Engineering

About Cadence

cadence.com

Headquarters

San Jose, California, United States

Company Size

10001+ employees

Founded

1988

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Cadence is a company specializing in electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries. Their tools enable design and verification of integrated circuits, systems on chips, and electronics systems, streamlining the development process for engineers and designers. With a commitment to innovation and excellence, Cadence empowers companies to enhance product performance and reduce time to market through advanced simulation, verification, and design tools.