Sr Staff /Staff Engineer, RTL Design

This role involves the front-end implementation of SERDES high-speed interface PHY/Controller designs and RTL development, including linting, CDC, and low-power checks. The engineer will collaborate with verification teams on test plans, manage timing constraints, and deliver synthesized netlists while supporting SoC integration and chip-level debugging. Experience with high-speed protocols like PCIe and UCIe, along with DFT insertion and ATPG analysis, is essential for meeting automotive coverage targets.