Sr. Staff Timing Engineer
Marvell Technology(2 months ago)
About this role
The ASIC design engineer at Marvell is responsible for the post RTL design flow, which includes block and chip level synthesis, timing closure, DFT generation, and ECOs. The role requires collaboration with design teams to enhance SerDes IP solutions and provide ongoing support for product teams throughout the design lifecycle.
Required Skills
- ASIC Design
- Synthesis
- Timing Closure
- DFT Generation
- Team Collaboration
Qualifications
- Bachelor’s Degree in Computer Science
- Electrical Engineering
- Master’s Degree
- PhD in Computer Science
- Electrical Engineering
About Marvell Technology
marvell.comDesigned for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
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