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SSG Design Engineering Intern (Fall 2026) at Cadence - ApplyBlast

SSG Design Engineering Intern (Fall 2026)

Cadence

3 months ago

4.0 on Glassdoor

San Jose, CA

Onsite

Full Time

Intern

0 applicants

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About this role

A Design Engineering Intern at Cadence joins the Silicon Solutions Group to work on Digital Design or Design Verification tasks for the Janus NoC IP product. The role involves RTL implementation in System Verilog, developing UVM test plans, scripting verification flows, and collaborating with design and physical design teams. Candidates will utilize EDA tools to study timing, area, and power goals while gaining hands-on experience in semiconductor design.

Responsibilities

Implement RTL logic in System Verilog for micro-architecture
Develop functional tests and verification monitors using UVM
Run synthesis and place and route to optimize timing and power
Debug failures and analyze coverage information for verification
Collaborate with design and physical design teams on NoC projects

Skills

About Cadence

cadence.com

Headquarters

San Jose, California, United States

Company Size

10001+ employees

Founded

1988

View Profile

Cadence is a company specializing in electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries. Their tools enable design and verification of integrated circuits, systems on chips, and electronics systems, streamlining the development process for engineers and designers. With a commitment to innovation and excellence, Cadence empowers companies to enhance product performance and reduce time to market through advanced simulation, verification, and design tools.