Staff Digital Verification Engineer

We are seeking a highly motivated Staff Digital Verification Engineer with 6-10 years of experience in ASIC/SoC verification to lead verification efforts across IP, subsystem, and SoC-level projects. The role involves independently architecting and developing reusable verification environments using System Verilog and UVM, creating test cases, and debugging complex RTL and gate-level issues. The position requires collaboration with design, DFT, and architecture teams to resolve issues and support sign-off activities.