Staff Engineer, DDEG Design Methodology

This role involves complete ownership of verification and end-to-end analysis for sophisticated full chip gate level custom designs, including advanced low power and power management technologies across DDR and LPDDR categories. The position requires leveraging AI-based tools and automation frameworks to accelerate verification cycles, improve debug efficiency, and validate AI outputs before integration into design decisions. The engineer will collaborate with global teams to develop verification methodologies, environments, and test benches for advanced DRAM and emerging memory products.