Staff System Validation Engineer
SiFive(2 months ago)
About this role
The RISC-V System Engineer (FPGA Execution) on the CoreIP team will develop, deploy, and support emulation and FPGA environments to enable silicon and software bring-up. The role involves collaborating with cross-functional teams to define emulation test strategy and frameworks, implement test plans, and debug complex hardware, software, and silicon design issues. The engineer will establish hardware and software readiness on emulation platforms for silicon validation.
Required Skills
- FPGA
- Emulation
- Debugging
- SoC Architecture
- Processor Architecture
- Linux
- Design Verification
- System Validation
- Test Planning
- Failure Analysis
+5 more
About SiFive
sifive.comAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
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