SiFive
The role involves building and maintaining modular flows for Synopsys ZeBu models, performing root cause and failure analysis on RISC‑V CPU hardware and software, and developing Python scripts to automate debug workflows. The engineer will work cross‑functionally with software and validation teams, leveraging FPGA platforms and Linux environments.
Headquarters
Santa Clara, California, United States
Company Size
501-1000 employees
Founded
2015
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for SiFive.
SiFive didn’t post a salary, so this is our estimate from similar listings.
10% above the average for this role
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