Technical Lead Design Verification Engineer
Astera Labs(10 days ago)
About this role
A Technical Lead Design Verification Engineer at Astera Labs leads verification efforts for complex SoC and silicon products used in server, storage, and networking applications. The role supports the company’s rack-scale AI connectivity solutions and collaborates across hardware and software teams. The position is based in Canada and requires immediate availability and work authorization.
Required Skills
- UVM
- C++
- System Verilog
- DPI/PLI
- Python
- Perl
- Constrained Random
- Assertions
- Coverage Analysis
- Verification IP
+5 more
Qualifications
- Bachelor's in Electrical Engineering
- Master's Preferred
About Astera Labs
asteralabs.comAstera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.
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