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Technology Lead-Memory Layout at Infosys - ApplyBlast

Technology Lead-Memory Layout

Infosys

2 days ago

Vancouver, British Columbia, Canada

Onsite

Full Time

Senior

0 applicants

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About this role

The Technology Lead-Memory Layout role involves collaborating with Registers and Memory Arrays and Memory data path layout and design engineers to create optimal layouts based on provided schematics. The position requires strong expertise in compiler/custom memory layout design, memory leafcell library creation, and optimized layout techniques for performance. Candidates must have hands-on experience with FinFET technology, advanced node processes, and physical verification tools like Cadence Virtuoso and Calibre.

Responsibilities

Create optimized memory layout designs from schematics
Collaborate with circuit teams to develop best layouts
Perform physical verification and debug using DRC LVS and ERC

Skills

About Infosys

infosys.com

Headquarters

Electronics City, Karnataka, India

Company Size

10001+ employees

Founded

1981

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Infosys is a global leader in next-generation digital services and consulting. It helps enterprises navigate digital transformation through IT services, consulting, and digital technologies, delivering solutions across cloud, analytics, automation, AI, and software engineering. With a vast global delivery network and industry-focused capabilities, Infosys partners with clients to drive innovation, efficiency, and resilient operations. The brand mantra Navigate Your Next underscores its mission to guide customers from their current state to their aspirational future.