Verification Planning & Execution

This role involves defining comprehensive verification strategies and developing scalable SystemVerilog/UVM-based environments for block-level, subsystem-level, and SoC-level verification. The position requires leading end-to-end verification of large SoCs, including interconnect, cache coherency, and low-power verification, while driving coverage closure and sign-off. It also entails providing technical leadership, mentoring engineers, and collaborating with design teams to resolve complex debug issues.