Yield Enhancement Defect Engineer

The Yield Enhancement Defect Engineer at TSMC Washington bridges the gap between raw process data and customer satisfaction by identifying, analyzing, and eradicating physical or electrical defect sources that limit wafer yields. This role involves using advanced metrology, data analytics, and cross-departmental collaboration to prevent production line deviations and optimize mature CMOS process nodes. The position requires close partnership with global customers and internal engineering teams to drive continuous improvement and maintain manufacturing performance.