Analog Layout Engineer

The Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits, including SerDes, ADCs, DACs, and PLLs. The role involves creating block-level and chip-top-level floor plans, managing hierarchical block integration, and addressing layout-dependent effects for parasitic and noise control. The position requires ensuring complete closure on DRC, LVS, ERC, antenna rules, and EM/IR reliability checks. Candidates should have 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes.